An 8b 250MS/s 0.13A mu m CMOS ADC using variable references for VGA-to-WUXGA scaler chips

作者：Park Hye Lim; Myung Sung Meen; Kim Younglok^*; Lee Seung Hoon

来源：Analog Integrated Circuits and Signal Processing, 2012, 73(1): 233-242.

DOI：10.1007/s10470-012-9900-1

• ADC
• Pipeline
• Low power
• Scaler
• Variable voltage reference
• Two-step reference selection

This work proposes an 8b 250MS/s 0.13A mu m CMOS two-step pipeline ADC using variable references for VGA-to-WUXGA scaler chip applications. The input sample-and-hold amplifier employs MOS capacitor-based gate-bootstrapping circuits to keep the on-resistance of sampling switches constant and to sample wide-band wide-range variable inputs with least distortion. The capacitors of the proposed multiplying D/A converter are laid out in a high matching one-dimensional symmetric shape rather than the conventional common-centroid topology to save chip area. The proposed on-chip current and voltage reference circuits generate variable bottom-side reference voltages with a fixed top-side reference using a single external voltage for processing wide-range variable analog inputs. The two-step reference selection scheme reduces considerably power and area in the last-stage 5b flash ADC. The prototype ADC in a 0.13A mu m CMOS demonstrates measured differential and integral non-linearities within 0.35 and 0.54 LSB, respectively. The ADC shows a maximum SNDR and SFDR of 44.4 and 56.1 dB at 250 MS/s, respectively. The ADC with an active die area of 0.72 mm(2) consumes 58.8-62.4 mW depending on input modes at 250 MS/s and 1.2 V.

• 出版日期2012-10