Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

作者：Cortes I^*; Fernandez Martinez P; Flores D; Hidalgo S; Rebollo J

来源：Semiconductor Science and Technology, 2008, 23(1): 015009.

DOI：10.1088/0268-1242/23/1/015009

This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (R(on)) value maintaining the same voltage capability. The increment of the N(+) source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low Ron results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.

• 出版日期2008-1