A Fast JPEG2000 Encoder That Preserves Coding Efficiency: The Split Arithmetic Encoder

作者：Varma Krishnaraj^*; Damecharla Hima B; Bell Amy E; Carletta Joan E; Back Godmar V

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2008, 55(11): 3711-3722.

DOI：10.1109/TCSI.2008.927221

• Context-state adaptation
• embedded block coder with optimal truncation (EBCOT)
• field-programmable gate array (FPGA)
• JPEG2000
• MQ coder
• multithreading

Embedded block coding, i.e., embedded block coder with optimal truncation (EBCOT) tier-1, is the most computationally intensive part of the JPEG2000 image coding standard. Past research on fast EBCOT tier-1 hardware implementations has concentrated on cycle-efficient formation. These pass-parallel architectures require that JPEG2000's three mode switches be turned on; thus, coding efficiency is sacrificed for improved throughput. In this paper, a new fast EBCOT tier-1 design is presented: It is called the split arithmetic encoder (SAE) process. The proposed process exploits concurrency to obtain improved throughput while preserving coding efficiency. The SAE process is evaluated using the following three methods: I clock cycle estimation, multithreaded software implementation, and FPGA hardware implementation. All three methods achieve throughput improvement; the hardware implementation exhibits the largest speedup, as expected. Them benefits of evaluating a proposed process (algorithm) from different perspectives are illustrated.

• 出版日期2008-12
• 单位美国弗吉尼亚理工大学(Virginia Tech)