摘要

This paper presents a physical explanation of the AM/PM distortion of a Si LDMOS based Doherty PA. Contrary to what is observed in single-ended mode operation, the Doherty AM/PM characteristic does not present the monotonic phase-lagging behavior for all input power levels. Instead, a phase plateau or even a phase-leading behavior is observed when the peaking PA enters into operation. It was found that the nonlinear C-ds and the input C-gd,C-Miller capacitances, along with the Doherty load modulation are the main responsibles for this Si LDMOS Doherty PAs' behavior. This was validated using a 700W, 1.8 GHz asymmetric Doherty PA using 230W Si LDMOS transistors for the carrier and peaking PAs.

  • 出版日期2016