Systematic Design Space Exploration of Floating-Point Expressions on FPGA

作者：Mahzoon Alireza; Alizadeh Bijan^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64(3): 274-278.

DOI：10.1109/TCSII.2016.2596800

• Design space exploration
• field-programmable gate array (FPGA)
• floating point
• high-level synthesis (HLS)

In this brief, we propose novel methods to systematically explore the design space of floating-point expressions on a field-programmable gate array in order to extract a nondominated set that covers the whole design space in terms of the accuracy, area, and run-time numbers. We first introduce a regular selection method that consists of two main phases: 1) generating equivalent expressions and 2) using a Pareto algorithm to extract a nondominated set. Then, we introduce a fast selection method in which two phases are composed in order to speed up the optimization process, while the quality of the final results does not change significantly. The results show that regular selection enjoys up to a 35.3% run-time improvement in comparison with the state-of-the-art techniques. Furthermore, the fast selection method is approximately 45x faster than the regular selection.

• 出版日期2017-3