A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs

作者：Serafy Caleb^*; Shi Bing; Srivastava Ankur

来源：Integration, the VLSI Journal, 2014, 47(3): 307-317.

DOI：10.1016/j.vlsi.2013.11.004

• TSV coupling
• TSV shielding
• 3D-IC
• Vertical integration

In 3D ICs, through-silicon-vias (TSVs) can suffer from cross coupling if signal integrity is not considered during the design process. In this paper, coupling between TSVs is modeled, and a chip-scale TSV shielding scheme is presented. A geometric model is developed to estimate TSV coupling. The low complexity of the geometric model makes it practical for chip-scale shield placement optimization. Two shield placement algorithms are presented and compared to standard shield placement techniques that use a high complexity circuit model of coupling. Results show that our algorithms are able to reduce the total cross coupling in a layout on average 111%/129% more than standard methods.

• 出版日期2014-6