A 10-bit 1.2 GS/s 45 mW time-interleaved SAR ADC with background calibration

作者：Xu Dai-guo^*; Pu-Jie; Xu Shi-liu; Zhang Zheng-ping; Chen Kai-rang; Cheng Yi-yi; Zhang Jun-an; Wang Jian-an

来源：IEICE Electronics Express, 2018, 15(3): 20171235.

DOI：10.1587/elex.15.20171235

• analog-to-digital converter (ADC)
• time-interleaved ADC
• successive-approximation-register (SAR) ADC
• meta-stability restrained
• high-linearity
• background calibration

A 10-bit 1.2 GS/s power efficient time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) is present in this paper. Substrate bias effect depression and output resistance stabilization techniques are provided to enhance the linearity of input buffer. Further, meta-stability restrained trigger comparator is used to enhance the ENOB (effective number of bits) of SAR ADC. Additionally, a digital background calibration technique is proposed to suppress the inter-channel gain, offset and timing skew mismatches. To demonstrate the proposed techniques, a design of time-interleaved SAR ADC is fabricated in 55-nm CMOS technology, consuming 45 mW from 1.2 V power supply with a SNDR of 50 dB and SFDR of 60 dB. The proposed ADC core occupies an active area of 0.84 mm(2), and the corresponding FoM is 145 fJ/conversion-step with Nyquist rate.

• 出版日期2018-2-10
• 单位电子科技大学