A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

作者：Rodoni Lucio^*; von Bueren George; Huber Alex; Schmatz Martin; Jaeckel Heinz

来源：IEEE Journal of Solid-State Circuits, 2009, 44(7): 1927-1941.

DOI：10.1109/JSSC.2009.2021913

• Clock and data recovery (CDR)
• CMOS analog integrated circuits
• current-mode logic (CML)
• delay-locked loop (DLL)
• high-speed serial link
• jitter tolerance

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2x-oversampling phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of +/- 615 ppm between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate < 10(-12) was verified up to 38 Gb/s using a 2(7)-1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s)the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90 nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 mm(2).

• 出版日期2009-7