A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

作者：Tikka Tero^*; Viitala Olli; Ryynanen Jussi

来源：Analog Integrated Circuits and Signal Processing, 2015, 83(1): 23-33.

DOI：10.1007/s10470-015-0501-7

• CMOS
• On-off-keying
• Transceiver design
• Wireless link

This paper presents a fully integrated 40-GHz transceiver designed for 2 Gbit/s short-range chip-to-chip communication link. The proposed architecture includes both the transmitter and the receiver and is optimized for on-off-keying modulation scheme. The transceiver design includes two variants, which can drive either a planar on-chip antenna or wire-bonded off-chip antenna. The performance comparison of these is given in the paper. A compact and energy-efficient technique has been adopted by directly modulating the oscillator in the transmitter. The receiver uses a self-mixing topology followed by transimpedance amplifier and a limiter chain. The detailed circuit descriptions as well as design trade-offs with simulation results in 65 nm CMOS are given. In addition, an example design modification to extend the modulation to 4-level amplitude shift keying is presented.

• 出版日期2015-4