A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of-250 dB

作者：Narayanan Aravind Tharayil; Katsuragi Makihiko; Kimura Kento; Kondo Satoshi; Tokgoz Korkut Kaan; Nakata Kengo; Deng Wei; Okada Kenichi; Matsuzawa Akira

来源：IEEE Journal of Solid-State Circuits, 2016, 51(7): 1630-1640.

DOI：10.1109/JSSC.2016.2539344

• CMOS
• DTC
• fast locking
• fractional-N synthesizer
• phase-locked loop (PLL)
• pipelined phase interpolator
• push-pull VCO
• short-current free
• sub-sampling PLL (SSPLL)

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-N PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-N PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-N mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.

• 出版日期2016-7