A High-level Synthesis Design Flow from ESL to RTL with Multi-parametric Optimization Objective

作者：Sengupta Anirban^*; Sedaghat Reza

来源：IETE Journal of Research, 2011, 57(2): 172-189.

DOI：10.4103/0377-2063.81741

• High-level synthesis design flow
• Multi-parametric optimization
• Portable devices
• Stringent operational constraints

High-level synthesis (HLS) has emerged as the most sophisticated way to bridge the gap between electronic system level (ESL) and its respective structural building block at the register transfer level (RTL). As the growth of system complexity rapidly increases, the gap between high level and RTL needs to be filled. Much advancement has been made in the area of HLS, but none of the works have focused on a formal design methodology that bridges the gap from ESL to RTL considering multi-parametric optimization requirements. This paper exclusively focuses on the formal steps required for multi-parametric optimized HLS design flow. This is significant for industrial projects as well as for the development of fully automated HLS tools for the current generation of portable devices and high-end applications. The design flow initiates with the mathematical model of the application, performs multi-objective design space exploration and finally shows all the steps necessary after exploration for the HLS design. This paper explicitly focuses on highlighting the design flow with optimization of three parameters area, execution time and power consumption during HLS design while working under the prerequisite of stringent operational constraints. The implementation of the proposed method on Field-programmable Gate Array and the chip layout generation will also be presented.

• 出版日期2011-4