Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology

作者：Mohammed Mahmood^*; Abugharbieh Khaldoon; Abdelfattah Mahmoud; Kawar Sanad

来源：AEU-International Journal of Electronics and Communications, 2016, 70(5): 568-577.

DOI：10.1016/j.aeue.2016.01.008

• CMOS
• MOSFET
• Saturation
• Subthreshold
• Voltage reference circuits

This work presents a detailed methodology to design a precision voltage reference circuit using MOSFET devices. First, the I-V relations of saturation and subthreshold MOSFETs are presented along with the temperature dependency of these devices. Then, a step-by-step procedure on how to design the main building blocks of voltage reference circuits is discussed. The proper relations between these building blocks are detailed. Moreover, circuit techniques to minimize the impact of process, voltage and temperature (PVT) variations on the voltage reference circuit are introduced. In order to verify the methodological approach, a novel circuit is presented. This new design has been simulated in the state-of-the-art 28 nm CMOS technology using Synopsys Custom Designer and HSPICE CAD tools. It generates a reference voltage of 252 mV with line sensitivity (LS) of 0.64% in a supply voltage range of 0.85-4.1 V. The temperature coefficient (TC) is 218.8 ppm/degrees C, through a temperature range of -15-80 degrees C. The power supply rejection ratio (PSRR) is -34 dB at 50 Hz and -48.6 dB at 1 MHz. Finally, the power consumption is 395 nW at nominal supply voltage. The process variations coefficient is 0.19%, and the peak-to-peak output noise is 3.08 mu V/(Hz)(1/2) at 10 Hz.

• 出版日期2016