An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits

作者：Wang Dong^*; Chan Pak Kwong

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(5): 958-968.

DOI：10.1109/TVLSI.2018.2794763

• Current reference circuit
• mismatch model
• process variation
• stress effect
• voltage reference circuit

This paper presents a new electrical-based stress model that addresses the stress effect in the nanometer CMOS devices. As such, the electrical performance of analog circuits in the presence of stress can be better predicted in statistical simulations. The model provides a random stress-induced offset. It relies on the current-resistance product-based random generators, which have the feature of Gaussian distribution, for nMOS and pMOS devices, respectively. The proposed model is simulated and validated through the analog voltage and current reference circuits which are realized in a UMC 65-nm CMOS process technology. Based on the comparison results, there is a good correlation between the model predicted results and the measured results of the stated reference circuits. This has demonstrated the effectiveness of the model. Finally, the model has confirmed that the stress-induced offset can be significantly reduced if the simplified dynamic element matching technique is applied in the reference circuit design.

• 出版日期2018-5
• 单位南阳理工学院