A Power Efficient BIST TPG Method on Don't Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

作者：Yuan Haiying^*; Guo Kun; Sun Xun; Mei Jiaping; Song Hongying

来源：Journal of Electronic Testing-Theory and Applications, 2015, 31(1): 43-52.

DOI：10.1007/s10836-015-5507-7

• Test data compression
• Scan-in test power dissipation
• Area overhead
• Don't care bit adjusting
• Hamming distance reordering

A power efficient BIST TPG method is proposed to reduce test power dissipation during scan testing. Before the test patterns are injected into scan chain, the test set adopts a series of preprocessed strategies including don't care bit based 2-D adjusting, Hamming Distance based 2-D reordering and test cube matrix based two transpose, all steps will be orderly executed in interspersed way. The six largest ISCAS'89 benchmark circuits verify the proposed method. Experimental results show that the switching activities are effectively reduced when the test set is loaded for on-chip scan testing. ASDFR with MT-filling scheme ensures high compression ratio, the scan-in test power dissipation is further decreased by don't care bit based 2-D adjusting and Hamming Distance 2-D reordering. In addition, the BIST TPG method with less test application time and smaller algorithm complexity can be widely applied to actual chip design without adding extra decoder area overhead.

• 出版日期2015-2
• 单位北京工业大学; 清华大学