摘要

A true class 'AB' fully differential current output stage with very high common mode rejection ratio is presented in this study. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by SPICE simulation in TSMC 0.18 mu m CMOS, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high common-mode rejection ratio (CMRR), high slew rate, high current drive capability, high output compliance, and very low power consumption while operating at power supply of +/- 0.9 V. The interesting results such as current drive capability of +/- 100 mu A, high output voltage swing of +/- 0.8 V, low static power consumption of 21 mu W, and very high CMRR of 84.5 dB is achieved utilizing standard CMOS technology. The performance of circuit at the presence of process and voltage variations evaluated through corner case and Monte Carlo analysis. The harmonic distortion is evaluated to investigate the circuit's linearity. The transient stepwise response analysis is also done to verify the stability of proposed class 'AB' FDCOS.

  • 出版日期2014-2

全文