A 10-bit 110 kS/s 1.16 mu W SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications

作者：Taherzadeh Sani Mohammad^*; Lotfi Reza; Nabki Frederic

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61(8): 584-588.

DOI：10.1109/TCSII.2014.2327373

• CMOS integrated circuits
• low power
• multichannel recording systems
• reduced area
• successive-approximation-register analog-to-digital converters (SAR ADCs)

A 10-bit 110-kS/s successive-approximation analog-to- digital converter (ADC) for multichannel biomedical applications is presented. In order to achieve low-power operation, the ADC utilizes a reduced-speed dynamic comparator, a low-complexity calibration technique, a hybrid single/differential digital-to-analog converter architecture, and an attenuation capacitor with low sensitivity to mismatch errors. Fabricated in 180-nm CMOS, this ADC consumes a total power of 1.16 mu W from 1.5 V/1.2 V analog/digital power supplies. The integral nonlinearity is between -1.23 LSB and 1.19 LSB, whereas the differential nonlinearity is between -0.71 LSB and 0.92 LSB. The ADC signal-to-noise-and-distortion ratio and spurious-free dynamic range are 56.1 and 67 dB with a 39.5-kHz sinusoid input, respectively. The ADC figure-of-merit is of 20 fJ per conversion step, which is very competitive, as compared with state-of-the-art ADCs in similar 180-nm CMOS technologies.

• 出版日期2014-8