科研之友
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摘要
A clock-harvesting receiver is presented, which extracts a 1.2-kHz clock embedded within the third-generation code-division multiple-access standard for the wake-up of a wireless sensor network. The energy-detection-based receiver was fabricated in 0.13-mu m CMOS and designed for low-power heavily duty-cycled operation. In active mode, the receiver has a measured sensitivity of -73 dBm while consuming only 298 mu W. The harvested-clock output has 7 mu s of root-mean-square jitter at the sensitivity level, which improves with higher received power. In sleep mode, the receiver consumes only 44 pW with a start-up time of 80 mu s.
- 出版日期2012-11
