A novel ADPLL design using successive approximation frequency control

作者：Eisenreich H; Mayr C; Henker S^*; Wickert M; Schueffny R

来源：Microelectronics Journal, 2009, 40(11): 1613-1622.

DOI：10.1016/j.mejo.2008.12.005

• PLL
• ADPLL

This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight reference cycles. ASICs in CMOS AMS 0.35 mu m and UMC 0.13 mu m have been manufactured and tested. Measurements show competitive results to state-of-the-art mixed-signal implementations.

• 出版日期2009-11