A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

作者：Park Kwanseo; Lee Jinhyung; Lee Kwangho; Choo Min Seong; Jang Sungchun; Chu Sang Hyeok; Kim Sungwoo; Jeong Deog Kyoon^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64(12): 1432-1436.

DOI：10.1109/TCSII.2017.2747148

• Adaptive equalizer
• clock and data recovery
• power efficient
• referenceless
• stream clock generator
• video interface receiver

A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta-sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm(2). The measured BER is less than 10-12 with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s.

• 出版日期2017-12