A 5th-order Sigma Delta modulator with combination of op-Amp and CBSC circuit for ADSL applications

作者：Zamani M^*; Taghizadeh M; Moghadasi M Naser; Virdee B S

来源：Analog Integrated Circuits and Signal Processing, 2012, 71(1): 143-150.

DOI：10.1007/s10470-011-9763-x

• Analog-to-digital data converter (ADC)
• Sigma delta modulator
• Comparator-based switched-capacitor circuit
• ADSL

In this letter, a 5th-Order single-loop low distortion Sigma-Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications. This structure, which uses integrator (CBSC-based) and IIR filter (op-amp-based) concurrently, has relatively fewer feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. To lower the power consumption of the modulator, the integrators are implemented with CBSC, the IIR filter block is implemented by single OTA, and a passive adder is used to realize the adder at the input of the 5-bit quantizer. The design purpose is minimizing the power consumption while the dynamic performance maintains high. As shown in the simulation result, for a 2-MHz signal bandwidth, the modulator achieves a dynamic range (DR) of 86.5 dB and a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with an oversampling ratio of 8. In addition it consumes 18.75 mW from a 1.8-V power supply at 32 MS/s, which obtains a figure of merit of 1.6e-3.

• 出版日期2012-4