A 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction technique

作者：Song Junyoung; Hwang Sewook; Kim Tae Chan; Kim Chulwoo

来源：Analog Integrated Circuits and Signal Processing, 2014, 79(1): 183-189.

DOI：10.1007/s10470-014-0258-4

• Wide-range PLL
• Integer-N PLL
• Spur reduction
• All-digital PLL

In this Letter, 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 ps(rms) at 1.5 GHz operation, and 3.991 ps(rms) at 400 MHz operation. The ADPLL occupies 0.088 mm(2), and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.

• 出版日期2014-4