A Reference-Less Single-Loop Half-Rate Binary CDR

作者：Jalali Mohammad Sadegh; Sheikholeslami Ali; Kibune Masaya; Tamura Hirotaka

来源：IEEE Journal of Solid-State Circuits, 2015, 50(9): 2037-2047.

DOI：10.1109/JSSC.2015.2429714

• Burst-mode CDR
• clock and data recovery
• cycle-slipping
• frequency detection
• gated VCO

This paper proposes a half-rate single-loop reference-less binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu's 65 nm CMOS, consumes 11 mW and improves the capture range by up to 6x when it is activated.

• 出版日期2015-9