A Programmable Divider with 50% Duty Cycle Unrelated to Dividing Cycle and Its Application to PLL

作者：Harada Yujiro^*; Yahara Mitsutoshi; Matsumoto Kinya; Fujimoto Kuniaki

来源：Electronics and Communications in Japan, 2016, 99(12): 84-90.

DOI：10.1002/ecj.11921

• programmable divider
• duty cycle
• phase locked loop

Recently, a signal processing using positive and negative edges of clock is used by memory and various digital devices to improve performance of digital circuits. In a signal processing using double edges, 50% duty cycle of an output signal of clock generator is an important factor. In this paper, we propose the programmable divider with which we always obtain the output signal of 50% duty cycle unrelated to the division ratio. The circuit configuration of this divider is very simple, and the operation is stable regardless of the increase in the division ratio. Also, when the proposed divider was included in the division ratio changeable-digital phase locked loop (DC-PLL), the output signal is always kept to 50% duty cycle regardless of the frequency of input signal. In experimental results using a field programmable gate array, we confirmed that this DC-PLL has the expected characteristics for phase error, lock-in range, and initial pull-in.

• 出版日期2016-12