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摘要
In this paper, a novel framework is introduced to estimate the max-delay variability in logic paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of the additional cycle time margin imposed by random (local) variations. The framework provides the designer with a deep insight into the main variability contributions, and the improvements allowed by prospective design modifications (e.g., logic restructuring and cell up-sizing). The proposed framework is applicable to a wide voltage range, from subthreshold to nominal. Our analysis shows that the popular fan-out-of-4 metric (FO4) fully captures the impact of technology, supply voltage, die-to-die, and voltage and temperature variations on the delay variability. On the other hand, the variability contribution due to random variations is accounted for by cell-specific coefficients having a clear physical meaning, and depending only on circuit-level parameters knobs (i.e., cell topology and transistor size). Accordingly, the proposed method completely decouples the effect of random variations from the impact of the process/voltage/temperature corner. The proposed approach has been validated in a range of technology generations (28, 40, and 65 nm) and voltages (from 0.3 to 1.2 V) through Monte Carlo simulations and silicon measurements (28 and 65 nm). Being adequately accurate compared with Monte Carlo simulations and silicon measurements, this framework eliminates time-consuming Monte Carlo simulations from the design loop, thus drastically facilitating design closure. Being its accuracy comparable to other state-of-the-art methods, the proposed framework can also be used for efficient automated statistical timing analysis of VLSI circuits.
- 出版日期2017-8
