A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

作者：Ku I Ning^*; Xu Zhiwei; Kuan Yen Cheng; Wang Yen Hsiang; Chang Mau Chung Frank

来源：IEEE Journal of Solid-State Circuits, 2012, 47(8): 1854-1865.

DOI：10.1109/JSSC.2012.2196731

• Analog-to-digital conversion
• CMOS analog integrated circuits
• subranging A/D converters
• switched capacitor circuits
• time-interleaved ADC (TI-ADC)

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital-controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm(2) chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08GHz input at 2.2GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC.

• 出版日期2012-8