An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

作者：Choi Kwang Hee^*; Shin Jung Bum; Sim Jae Yoon; Park Hong June

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56(9): 2055-2063.

DOI：10.1109/TCSI.2008.2011577

• All-digital phase-locked loop (ADPLL)
• digitally controlled oscillator (DCO)
• interpolation
• tri-state inverter
• wide range

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mu m CMOS process with the active area of 0.32 mm(2). The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.

• 出版日期2009-9