A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation- Register Analog-to-Digital Converter With Digital Calibration

作者：Liu Wenbo^*; Huang Pingli; Chiu Yun

来源：IEEE Journal of Solid-State Circuits, 2011, 46(11): 2661-2672.

DOI：10.1109/JSSC.2011.2163556

• Capacitor mismatch
• digital background calibration
• dynamic threshold comparison
• high linearity
• low power
• perturbation
• rail-to-rail swing
• redundancy
• SAR ADC

This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm(2) silicon area in a 0.13-mu m CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.

• 出版日期2011-11