Hysteresis analysis in excimer-laser-annealed low-temperature polycrystalline-silicon thin-film transistors

作者：Kim Yu Mi^*; Jeong Kwang Seok; Yun Ho Jin; Yang Seung Dong; Lee Sang Youl; Kim Moo Jin; Kwon Oh Seob; Jeong Chul Woo; Kim Jae Yong; Kim Sung Chul; Lee Ga Won

来源：Journal of the Society for Information Display, 2012, 20(7): 355-359.

DOI：10.1889/JSID20.7.355

• LTPS TFT
• excimer laser anneal
• hysteresis
• grain-boundary tap
• interface trap

To analyze the hysteresis phenomenon in p-channel low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs), the direct correlation between the hysteresis and the interface (N-it) and the grain-boundary trap density (N-trap) has been investigated. To fabricate LTPS TFTs with different electrical properties and trap types, the thickness of a-Si was varied from 30 to 80 nm and crystallized by the excimer-laser-anneal (ELA) method. The interface trap density is extracted from the subthreshold slope (SS) and low-high-frequency C-V analysis, while the grain-boundary trap density is extracted by the Levinson and Proano method. The LTPS TFTs with smaller hysteresis exhibited a lower trap density. From the correlation between extracted parameters, the hysteresis seems to be more dependent on N-it and decreases when the film thickness increases to 80 nm while the N-trap is almost the same in all devices.

• 出版日期2012-7