A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique

作者：Ono Koichi^*; Ohkawa Takeshi; Segami Masahiro; Hotta Masao

来源：IEICE - Transactions on Electronics, 2010, E93C(3): 288-294.

DOI：10.1587/transele.E93.C.288

• ADC
• folding
• interpolation
• reset
• averaging
• error correction

A 7 bit 10 Gsps Cascaded Folding ADC is presented This ADC employs cascaded folding architecture with 3-degree folders A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1 2 V and 2 5 V supplies and has a SNR of 38 dB

• 出版日期2010-3