A Translinear, Log-Domain FPAA on Standard CMOS Technology

作者：Fernandez Daniel^*; Martinez Alvarado Luis; Madrenas Jordi

来源：IEEE Journal of Solid-State Circuits, 2012, 47(2): 490-503.

DOI：10.1109/JSSC.2011.2170597

• Analog signal processing
• CMOS
• field-programmable analog array (FPAA)
• log-domain
• low power
• reconfigurable circuits
• translinear

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 x 5 RTC FPAA testchip was implemented in 0.35-mu m CMOS technology. A set of various circuit primitives, such as one-and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 mu W/TE and precision errors below 3%.

• 出版日期2012-2