摘要
A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 mu m CMOS process show that the phase noise is -109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.
- 出版日期2013-1