A 5 Gb/s, 10 ns Power-On-Time, 36 mu W Off-State Power, Fast Power-On Transmitter for Energy Proportional Links

作者：Anand Tejasvi^*; Elshazly Amr; Talegaonkar Mrunmay; Young Brian; Hanumolu Pavan Kumar

来源：IEEE Journal of Solid-State Circuits, 2014, 49(10): 2243-2258.

DOI：10.1109/JSSC.2014.2345764

• Burst mode
• digital regulator
• energy efficient
• energy proportional
• fast power-on
• I/O
• multiplying delay locked loop (MDLL)
• serial link
• transmitter

A fast power-on transmitter architecture that enables energy proportional communication for server and mobile platforms is presented. The proposed architecture and circuit techniques achieve fast power-on capability in voltage mode output driver by using fast-digital regulator, and in the clock multiplier by accurate frequency pre-setting and periodic reference insertion. To ease timing requirements, an improved edge replacement logic circuit for the clock multiplier is proposed. The proposed transmitter demonstrates energy proportional operation overwide variations of link utilization, and is therefore suitable for energy efficient links.
Fabricated in 90 nm CMOS technology, the voltage mode driver and the clock multiplier achieve power-on-time of only 2 ns and 10 ns, respectively. By using highly scalable digital architecture with accurate frequency pre-setting and instantaneous phase acquisition, the prototype MDLL-based clock multiplier achieves 10 ns (3 reference cycles) power-on-time, 2 ps(rms) long-term absolute jitter at 2.5 GHz output frequency. The proposed fast power-on transmitter architecture consumes 4.8 mW/36 mu W on/off-state power from 1.1 V supply, has 10 ns total power-on time, and achieves 100 effective data rate scaling (5 Gb/s-0.048 Gb/s), while scaling the power and energy efficiency by only 50 (4.8 mW-0.095 mW) and 2 (1-2 pJ/Bit), respectively. The proposed transmitter occupies an active die area of 0.3 mm(2).

• 出版日期2014-10