A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS

作者：Brenna Stefano; Bonfanti Andrea^*; Lacaita Andrea Leonardo

来源：Analog Integrated Circuits and Signal Processing, 2014, 81(1): 181-194.

DOI：10.1007/s10470-014-0384-z

• ADC
• Analog-to-digital conversion
• Nonlinearity
• Mismatch
• Asynchronous logic
• Successive approximation register

The conventional binary weighted array successive approximation register (SAR) analog-to-digital converter (ADC) is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even if it requires extra effort to design and simulate full custom fF or sub-fF capacitors. This paper presents the design and the optimization of an asynchronous fully-differential SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. The 10-bit converter prototype has been fabricated in a standard 0.13-mu m CMOS technology. At a 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and it's the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an active area of only 0.045 mm(2).

• 出版日期2014-10