A spatial sampling based 13.3 Gs/s sample-and-hold circuit

作者：Sun Jiwei^*; Wang Haibo; Wang Pingshan

来源：Review of Scientific Instruments, 2014, 85(9): 094707.

DOI：10.1063/1.4896123

This paper presents a high-speed sample-and-hold circuit (SHC) for very fast signal analysis. Spatial sampling techniques are exploited with CMOS transmission lines in a 0.13 mu m standard CMOS process. The SHC includes on chip coplanar waveguides for signal and clock pulse transmission, a clock pulse generator, and three elementary samplers periodically (L = 7.2 mm) placed along the signal propagation line. The SHC samples at 13.3 Gs/s. The circuit occupies an area of 1660 mu m x 820 mu m and consumes similar to 6 mW at a supply voltage of 1.2 V. The obtained input bandwidth is similar to 11.5 GHz.

• 出版日期2014-9