A reconfigurable processor architecture combining multi-core and reconfigurable processing units

作者：Yan, Like^*; Wu, Binbin; Wen, Yuan; Zhang, Shaobin; Chen, Tianzhou

来源：Telecommunication Systems, 2014, 55(3): 333-344.

DOI：10.1007/s11235-013-9791-1

• Multi-core
• Dynamic reconfiguration
• Processor architecture
• Reconfigurable computing

It's a promising way to improve performance significantly by adding reconfigurable processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. Reconfigurable logic is separated into RPUs logically, which are coupled with general purpose cores as co-processors via a full crossbar switch. An RPU Manager (RPU-M) is also designed to manage RPUs. To verify RMC, a simulation method based on the Simics and Virtex 5 FPGA is adopted, which simplifies the simulation and assures the evaluation accuracy of hardware function cores. Five workloads are selected to test RMC, including 3-DES, AES, SHA2, IDCT and JPEG_ENC. The experimental results show a 3.10 times average speedup over software implementation on the original multi-core, and the data and control communication overhead on RMC is acceptable.

• 出版日期2014-3
• 单位浙江大学