A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression

作者：Liao Fang Ren^*; Lu Shey Shi

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57(12): 946-950.

DOI：10.1109/TCSII.2010.2087992

• Charge pump (CP)
• current mismatch
• delay-locked loop (DLL)
• edge combiner
• frequency multiplier
• frequency synthesizer
• phase-locked loop (PLL)
• spur

A programmable edge-combining delay-locked loop (DLL) with fast switching transient and reduced output spur is presented in this work. With 12 delay cells adopted in the DLL, the programmable frequency-multiplied output can be quickly switched between x6, x3, and x2 without affecting the lock state of the DLL. Output spur is suppressed by reducing the DLL phase offset in the lock state, which is achieved by decreasing the charge-pump (CP) current during the idle interval of the phase detector. The proposed DLL frequency synthesizer, which has been realized in a CMOS 90-nm technology, consumes 20 mW at 1.2 V supply with the frequency-multiplied output covering from 0.45 to 5.4 GHz. For 850-MHz input clock, the phase noise at 1-MHz frequency offset after x6, x3, and x2 is -121.4, -127.4, and -129.7 dBc/Hz, respectively. The corresponding output spurs achieve -26.2, -36.8, and -39.2 dBc for x6, x3, and x2, which are 7.6, 5.9, and 15.4 dB lower than those using a conventional current-steering CP, respectively.

• 出版日期2010-12
• 单位中国科学院电工研究所