A 5-GHz Low-Power Low-Noise Integer-N Digital Subsampling PLL With SAR ADC PD

作者：Liu, Maliang; Ma, Rui; Liu, Shubin; Ding, Zhen; Zhang, Pan; Zhu, Zhangming^*

来源：IEEE Transactions on Microwave Theory and Techniques, 2018, 66(9): 4078-4087.

DOI：10.1109/TMTT.2018.2840987

• Digital phase-locked loop (DPLL)
• divider less
• phase detector (PD)
• subsampling
• successive-approximation register analog-to-digital converter (SAR ADC)

In this paper, we present a low-power low-noise integer-N divider-less digital phase-locked loop (PLL) with high resolution. Phase detection is performed by a proposed analog-todigital converter (ADC)-based time-to-digital converter composed of subsampling, charge pump (CP), time-domain variable-gain amplifier, and successive-approximation register (SAR) ADCs. Subsampling is well known for its high detection gain. The CP and the pulse generating circuit are also introduced to form the time-domain integral variable-gain amplifier, enhancing the resolution. An SAR ADC voltage signals into the digital domain, avoiding the use of analog filter which occupies large area. Moreover, compared to the conventional analog phase detectors, the SAR-ADC phase detector saves more area and power consumption. The novel PLL is implemented in a standard 65-nm CMOS process, occupying an area of 0.12 mm(2). It presents an in-band phase noise of -108 dBc/Hz and an rms jitter of 357 fs at the operating frequency of 5 GHz. In addition, the proposed ADC-PLL achieves a competitively good figure of merit of 243 dli with a power consumption of only 3.9 mW.

• 出版日期2018-9
• 单位西安电子科技大学