An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H

作者：Sin, Sai-Weng^*; Ding, Li; Zhu, Yan; Wei, He-Gong; Chan, Chi-Hang; Chio, U.-Fat; Seng-Pan, U.; Martins, R.P.; Maloberti, Franco

来源：36th European Solid State Circuits Conference, ESSCIRC 2010, 2010-09-14 To 2010-09-16.

DOI：10.1109/ESSCIRC.2010.5619890

• 65nm cmos
• Residual generation
• Residual generator
• SAR ADC
• Single stage
• Step time
• Subthreshold operation
• Time-interleaving

An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and subthreshold operation enables the use of a power-effective, single-stage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step.

• 出版日期2010
• 单位澳门大学