A novel model for computing the effective capacitance of CMOS gates with interconnect loads

作者：Huang, ZC^*; Kurokawa, A; Inoue, Y; Mao, JF

来源：IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A(10): 2562-2569.

DOI：10.1093/ietfec/e88-a.10.2562

• static timing analysis
• gate delay
• CMOS inverter
• effective capacitance
• interconnect loads

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C-eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C-eff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C-eff. The introduction of Integration Approximation results in C-eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-pi loads. Experimental results show a significant improvement in accuracy.

• 出版日期2005-10
• 单位上海交通大学