A templated programmable architecture for highly constrained embedded HD video processing

作者：Thevenin, Mathieu^*; Paindavoine, Michel; Schmit, Renaud; Heyrman, Barthelemy; Letellier, Laurent

来源：Journal of Real-Time Image Processing, 2019, 16(1): 143-160.

DOI：10.1007/s11554-018-0808-6

• SIMD
• VLIW
• Programmable
• Low silicon footprint
• Low-power

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacitiesseveral dozens of GOPs for real-time HD 1080p video streams. Today's embedded design constraints impose limitations both in terms of silicon budget and power consumptionusually 2mm2 for half a Watt. This paper presents the eISP architecture that is able to reach 188MOPs/mW with 94GOPs/mm2 and 378GOPs/mW using TSMC65-nm integration technology. This fully programmable and modular architecture, is based on an analysis of video-processing algorithms. Synthesizable VHDL is generated taking into account different parameters, which simplify the architecture sizing and characterization.

• 出版日期2019-2
• 单位中国地震局