A Compact Model for Single-Poly Multitime Programmable Memory Cells

作者：Li, Cong^*; Xu, Shun Qiang^*; Li, Jian Cheng^*; Chen, Ya Ling^*; Wang, Hong Yi^*

来源：IEEE Transactions on Electron Devices, 2016, 63(2): 675-683.

DOI：10.1109/TED.2015.2509603

• Compact model
• multitime programmable (MTP)
• single-poly
• standard CMOS process
• Verilog-A

A compact model for the single-poly multitime programmable (MTP) memory cells is presented in this paper for the first time. It is based on the charge balance approach, while the traditional old model is on the fixed capacitive coupling approach. The proposed cell model has been implemented by Verilog-A and integrated into commercial SPICE simulator. The model supports both dc and transient analyses, and the simulated results are consistent very well with those from device simulation and measurement, whereas the results by the traditional old model deviate substantially. Furthermore, the comprehensive optimization of the MTP cells is made feasible thanks to the new model, such as device size, high voltage ramp rate, and reliability prediction. As a result, this compact cell model will be very useful for the designers to evaluate and optimize a single-poly MTP cell.

• 出版日期2016-2
• 单位中国人民解放军国防科学技术大学