A Routing Approach to Reduce Glitches in Low Power FPGAs

作者：Dinh Quang^*; Chen Deming; Wong Martin D F

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(2): 235-240.

DOI：10.1109/TCAD.2009.2035564

• FPGA
• glitch reduction
• low power
• path balancing
• routing

This paper presents a novel approach to reduce dynamic power in field-programmable gate arrays (FPGAs) by reducing glitches during routing. It finds alternative routes for early-arriving signals so that signal arrival times at look-up tables are aligned. We developed an efficient algorithm to find routes with target delays and then built a glitch-aware router aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 27% reduction in glitch power is achieved, which translates into an 11% reduction in dynamic power, compared to the glitch-unaware versatile place and route's router.

• 出版日期2010-2