ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology

作者：Wang Chang Tzu^*; Ker Ming Dou

来源：IEEE Transactions on Electron Devices, 2010, 57(12): 3395-3404.

DOI：10.1109/TED.2010.2079530

• Bipolar CMOS DMOS (BCD) process
• electrostatic discharge (ESD)
• ESD protection
• latchup

An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-mu m 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.

• 出版日期2010-12