A 25-Gb/s 5-mW CMOS CDR/Deserializer

作者：Jung Jun Won^*; Razavi Behzad

来源：IEEE Journal of Solid-State Circuits, 2013, 48(3): 684-697.

DOI：10.1109/JSSC.2013.2237692

• Charge steering
• clock and data recovery
• deserializer
• phase detecter

The demand for higher data rates in serial links has exacerbated the problem of power consumption, motivating extensive work on receiver and transmitter building blocks. This paper presents a half-rate clock and data recovery circuit and a deserializer that employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz jitter frequency.

• 出版日期2013-3