A fast-locking PLL with all-digital locked-aid circuit

作者：Kao Shao Ku^*; Hsieh Fu Jen

来源：International Journal of Electronics, 2013, 100(2): 245-258.

DOI：10.1080/00207217.2012.692631

• PLL
• fast locking
• dual loop
• locked aid
• frequency detector
• phase detector

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 mu m CMOS process with a 3.3?V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

• 出版日期2013-2-1
• 单位长春大学