A Low Power Frequency Synthesizer for 60-GHz Wireless Personal Area Networks

作者：Khan Nawreen^*; Hossain Masum; Law K L Eddie

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2011, 58(10): 622-626.

DOI：10.1109/TCSII.2011.2164157

• Delay-locked loop (DLL)
• edge combiner
• frequency synthesizers
• injection-locked oscillator (ILO)
• phase-locked loop (PLL)

In this brief, a 60-GHz frequency synthesizer for wireless personal area networks is designed using 0.13-mu m CMOS technology. The synthesizer operates at 60 GHz with phase noises of -98, -117, and -128 dBc/Hz at 1-, 10-, and 40-MHz frequency offsets, respectively. The 60-GHz clock is generated by combining a phase-locked loop (PLL) and an injection-locked oscillator. The PLL provides frequency tuning of the 60-GHz voltage-controlled oscillator (VCO) using replica tuning. A pulse train is generated using a novel passive delay-locked loop and a CMOS pulse generator. This pulse train is then used for filtering the phase noise of 60-GHz VCO up to a high offset frequency. The total power consumption of the frequency synthesizer is 57 mW with a 1.2-V power supply.

• 出版日期2011-10