摘要

A digitally-programmable circuit is proposed to provide high-voltage protection at start-up, overload, and supply loss conditions in continuous-time passive-active sigma delta ADCs implemented in low-voltage nanometer CMOS technologies. The circuit optimizes the common-mode level at the input stage of the ADC enabling it to interface with input levels beyond its own supply voltage with no impact on device reliability or distortion levels, and minimum impact on area and noise performance, which provides maximum flexibility in the ADC usage. The proposed circuit along with the full ADC is implemented in a typical 65 nm CMOS technology.

  • 出版日期2010-2

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