A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor

作者：Choi Jaehyouk^*; Kim Stephen T; Kim Woonyun; Kim Kwan Woo; Lim Kyutae; Laskar Joy

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(4): 701-705.

DOI：10.1109/TVLSI.2009.2036433

• Clock generator
• delay cell
• delay locked loop (DLL)
• multiplication factor
• programmable

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18-mu m CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm(2).

• 出版日期2011-4