A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA

作者：Rosa Leandro de Souza^*; Dasu Aravind; Diniz Pedro C; Bonato Vanderlei

来源：Journal of Signal Processing Systems for Signal Image and Video Technology, 2018, 90(3): 357-369.

DOI：10.1007/s11265-017-1243-9

• Fixed-point
• Floating-point
• Kalman Filter
• Systolic Arrays
• FPGA

The Extended Kalman Filter (EKF) computation is a core task for the simultaneous localization and mapping (SLAM) problem in autonomous mobile robots. The SLAM problem involves operations over high dimension data sets, requiring high throughput and performance, given the real-time nature of the robotics, control-decision algorithm this task is a part of. The lightweight and power restricted computing environments in mobile robotics requires customized processing systems such as Field-Programmable Gate Arrays (FPGAs). This work presents an arithmetic precision analysis and a Faddeev algorithm to calculate the Schur's Complement hardware architecture implementation for the EKF-SLAM using a Systolic Array (SA). While it is widely believed that fixed-point implementations of arithmetic operations lead to area and performance benefits on FPGAs, the results in this article reveal that each Processing Element (PE) in the SA consumes 25% more logic and about 30% more register resources for the fixed-point 13.23 representation than if using the IEEE-754 single precision floating-point format. In addition, for FPGA devices with hardware support for key components of floating-point computations, a single PE floating-point implementation can achieve a maximum frequency up to 50% higher than a corresponding fixed-point implementation for the same relative numeric errors.

• 出版日期2018-3