A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS

作者：Zhang Dai^*; Alvandpour Atila^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(3): 244-248.

DOI：10.1109/TCSII.2015.2482618

• Digital error correction
• nonbinary-weighted
• redundancy
• successive approximation register (SAR) analog-to-digital converter (ADC)
• successive approximation

This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

• 出版日期2016-3